（Information, Production, and Systems Center）
Research Results Outline：The Dynamic Partial Reconfiguration (DPR) feature of reconfigurable devicesThe Dynamic Partial Reconfiguration (DPR) feature of reconfigurable devices (such as FPGA) allows multiple tasks to be imple...The Dynamic Partial Reconfiguration (DPR) feature of reconfigurable devices (such as FPGA) allows multiple tasks to be implemented on a single device simultaneously. The task placement problem comes with the DPR feature and affects the device performance directly. This year, our research addresses the task placement problem for the special task model and device model.Task placement problem for multi-shape task modelTraditional task mapping algorithms simplify the task as a rectangular shape, which results in the additional internal unused areas, thus wasting a significant portion of FPGA resources. In our research, a new task mapping algorithm for the multi-shape tasks is proposed to address the resource waste problem. The result is published in IEEE International Parallel and Distributed Processing Symposium Workshops.Task placement problem on three-dimensional dynamic partial reconfigurable devicesThree-dimensional (3D) integration technology provides a great opportunity for reconfigurable devices to increase device performance. Nevertheless, there is no efficient data structure and task placement algorithm to manage 3D dynamic partial reconfigurable (DPR) resources in literature. Inefficient algorithms limit the performance of 3D DPR devices. Our research addresses the issue of the 3D task placement problem by proposing a novel data structure to manage 3D resources. The result is published in IEEE Access.