Last Modified2017/02/01

Name

SHI, Youhua

Official Title

Professor

AffiliationFaculty of Science and Engineering

(School of Fundamental Science and Engineering)

Contact Information

Mail Address

Mail Address
shi@waseda.jp

Address・Phone Number・Fax Number

Address
3-4-1 Okubo, Shinjuku, Tokyo 169-8555 Japan
Phone Number
+81-3-5286-3400

URL

Web Page URL

http://www.eps.sci.waseda.ac.jp/teachers_popup/shi.html

Grant-in-aids for Scientific Researcher Number
70409655

Sub-affiliation

Sub-affiliation

Faculty of Science and Engineering(Graduate School of Fundamental Science and Engineering)

Educational background・Degree

Educational background

-2005 Waseda University Graduate School, Division of Engineering

Academic Society Joined

IPSJ

IEICE

Award

IEEK Best Paper Award

2012/11

Research Field

Keywords

Reliable and fault-tolerant computing, Cryptography, Video Processing

Grants-in-Aid for Scientific Research classification

Informatics / Calculations of Informatics / Computer system

Engineering / Electrical and electronic engineering / Electron device/Electronic equipment

Research interests Career

LSI design and CAD

Current Research Theme Keywords:LSI, SoC, CAD

Individual research allowance

Paper

Floorplan Driven Architecture and High-level Synthesis Algorithm for Dynamic Multiple Supply Voltages

Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, and Nozomu Togawa

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Vol. E96-A(No. 12) p.2597 - 26112013/12-

Scan-based attack on AES through round registers and its countermeasure

Youhua Shi, N. Togawa, and M. Yanagisawa

IEICE Trans. on Fundamentals of Electronics Communications and Computer Science Vol. E95-A(No.12) p.2338 - 23462012/12-

DOI

MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures

Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa

IEICE Electronics Express 9(17) p.1414 - 14222012/09-

DOI

Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis

Shi, Youhua;Togawa, Nozomu;Yanagisawa, Masao;Ohtsuki, Tatsuo

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 20(1) p.176 - 1812012-2012

DOIWoS

Detail

ISSN:1063-8210

Improved Launch for Higher TDF Coverage With Fewer Test Patterns

Shi, Youhua;Togawa, Nozomu;Yanagisawa, Masao;Ohtsuki, Tatsuo

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 29(8) p.1294 - 12992010-2010

DOIWoS

Detail

ISSN:0278-0070

X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction

Youhua Shi, Nozomu Togawa, Masao Yanagisawa and Tatsuo Ohtsuki

IEICE Trans. on Fundamentals of Electronics Communications and Computer Science E92-A(12) p.3119 - 31272009/12-

DOI

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n)

Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, and Tatsuo Ohtsuki

IEICE Trans. on Fundamentals of Electronics Communications and Computer Science E92-A(9) p.2304 - 23172009/09-

DOI

A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, and Tatsuo Ohtsuki

IEICE Trans. on Fundamentals of Electronics Communications and Computer Science E91-A(12) p.3514 - 35232008/12-

DOI

A Secure Test Technique for Pipelined Advanced Encryption Standard

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, and Tatsuo Ohtsuki

IEICE Trans. on Fundamentals of Electronics Communications and Computer Science E91-D(3) p.776 - 7802008/03-

DOI

Scan-Based Attack on AES through Round Registers and Its Countermeasure

Shi, Youhua;Togawa, Nozomu;Yanagisawa, Masao

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A(12) p.2338 - 23462012-2012

DOIWoS

Detail

ISSN:0916-8508

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design

Abe, Shin-ya;Shi, Youhua;Usami, Kimiyoshi;Yanagisawa, Masao;Togawa, Nozomu

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A(7) p.1376 - 13912015-2015

DOIWoS

Detail

ISSN:1745-1337

An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead

Yoshida, Shinnosuke;Shi, Youhua;Yanagisawa, Masao;Togawa, Nozomu

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A(7) p.1406 - 14182015-2015

DOIWoS

Detail

ISSN:1745-1337

Secure Scan Architecture Using State Dependent Scan Flip-Flop with Key-Based Configuration on RSA Circuit

ATOBE Yuta;SHI Youhua;YANAGISAWA Masao;TOGAWA Nozomu

112(247) p.95 - 1002012/10-2012/10

CiNii

SAAV:Energy-efficient High-level Synthesis Algorithm targeting Adaptive Voltage Huddle-based Distributed Register Architecture with Dynamic Multiple Supply Voltages

ABE Shin-ya;SHI Youhua;USAMI Kimiyoshi;YANAGISAWA Masao;TOGAWA Nozomu

112(320) p.135 - 1402012/11-2012/11

CiNii

An Energy-efficient ASIP Synthesis Method Using Scratchpad Memory and Code Placement Optimization

SHIMADA Yoshinori;SHI Youhua;TOGAWA Nozomu;YANAGISAWA Masao;OHTSUKI Tatsuo

Technical report of IEICE. VLD 110(432) p.25 - 302011/02-2011/02

CiNii

Detail

ISSN:09135685

Outline:In this paper, we propose an energy-efficient ASIP synthesis method using scratchpad memory. Due to the fact that a significant amount of power is consumed in the instruction memory, how to develop energy-efficient memory structure becomes important in reducing the overall power consumption of the system. Our method is based on the idea of using scratchpad memory with code placement optimization. The proposed memory architecture can copy data from instruction memory to scratchpad meory under the control of on-chip program counter. With an inputted application CFG, the proposed code placement optimization is used to decide both the code allocations and the required scratchpad memory size for energy minimization. By doing this, the total energy consumption could be reduced as the number of instruction memory accesses is reduced. Experimental results on Mediabench are included to show the effectiveness of the proposed method, in which on average 47.9% energy consumption could be reduced.

A-3-4 AES Cryptosystem Using Clock Falling Edge Against DFA

Igarashi Hiroaki;Shi Youhua;Yanagisawa Masao;Togawa Nozomu

Proceedings of the Society Conference of IEICE 20122012/08-2012/08

CiNii

A-3-5 Secure Scan Architecture Using State Dependent Scan Flip-Flop with Feedback

Atobe Yuta;Shi Youhua;Yanagisawa Masao;Togawa Nozomu

Proceedings of the Society Conference of IEICE 20122012/08-2012/08

CiNii

Secure Scan Architecture Using State Dependent Scan Flip-Flop with Key-Based Configuration against Scan-Based Attack

ATOBE Yuta;SHI Youhua;YANAGISAWA Masao;TOGAWA Nozomu

Technical report of IEICE. VLD 112(320) p.45 - 502012/11-2012/11

CiNii

Detail

ISSN:0913-5685

Outline:Secure cryptographic LSIs is intensively used in order to perform confidential operation. Scan test has become the most widely adopted test technique to ensure the correctness of manufactured LSIs, in which through the scan chains the internal states of the circuit under test (CUT) can be controlled and observed externally. However, scan chains using scan test might carry the risk of being misused for secret information leakage. Therefore a secure scan architecture using SDSFF (State Dependent Scan Flip-Flop) against scan-based attack which achieves high security without compromising the testability is proposed. In SDSFF, there is a problem which is the update timing of the latch which added to the scan FF. In this paper, we propose the update timing to online test without sacrificing the security. In our method, the latches are updated by result which the value of KEY which decided when designed compared with any FFs in a scan chain. We show that by using proposed method, neither the secret key nor the testability of vairous crypto circuits implementation is compromised, and the effectiveness of the proposed method. Experimental results on various crypto implementations show the effectiveness of the proposed method.

A Comsideration on Hardware Trojan Detection Specifying Trojan Path

Atobe Yuta;Shi Youhua;Yanagisawa Masao;Togawa Nozomu

Proceedings of the Society Conference of IEICE 20132013/09-2013/09

CiNii

Data Recoverable AES Circuit Against Differential Fault Analysis

Taniguchi Hiroaki;Shi Youhua;Togawa Nozomu;Yanagisawa Masao

Proceedings of the Society Conference of IEICE 20132013/09-2013/09

CiNii

Local pulse generation in variable stages pipeline designs for low energy consumption

Takayuki Nii;Youhua Shi;Nozomu Togawa;Kimiyoshi Usami;Masao Yanagisawa

2014(2) p.1 - 62014/09-2014/09

CiNii

Detail

ISSN:09196072

Outline:The increase of energy consumption due to improved performance has become a problem in the mobile terminal, and various low energy design techniques have been proposed. Variable Stages Pipeline(VSP) technique is one of them, which can reduce glitches by using a special LDS-cell(Latch D-FF selector-cell). However, glitches that occur during the low clock phase will still be propagated to next stages. In this paper, we propose a method for variable stages pipeline designs by applying local pulse generation and clock gating in LE mode for further energy reduction. We implemented the proposed method to a multiplier and experimental results show that the energy is reduced by 3.08% when compared to conventional VSP.

Latch-based AES Encryption Circuit Against Fault Analysis

SHI Youhua;TANIGUCHI Hiroaki;TOGAWA Nozomu;YANAGISAWA Masao

Technical report of IEICE. VLD 113(454) p.37 - 422014/02-2014/02

CiNii

Detail

ISSN:0913-5685

Outline:In general, cryptography is considered to be secure because it is based on complicated mathematical theories. In recent year, however, attacks on not crypto algorithms but hardware implementations such as fault analysis methods have posed new security threats. Cryptographic circuits are prone to fault analysis that intend to retrieve secret data by means of malicious fault injection. Clock-adjustment, voltage change, and laser manipulation can be used to inject malicious faults during the execution of a crypto circuit. As countermeasures against fault analysis, area-redundant methods such as triple modular redundant(TMR) and timing-redundant methods have been proposed at the cost of area or throughput. In this paper, we proposed a latch-based AES encryption circuit, with 18.1% area overhead and 5% throughput improvement, which can detect all the possible errors during the fault analysis region of clock glitch based fault analysis. In addition to fault analysis detection, the proposed method can also prevent the transmission and the use of erroneous results, and then can guarantee the correctness of the final encrypted outputs.

Secure scan design using improved random order scans and its evaluations

OYA Masaru;ATOBE Yuta;SHI Youhua;YANAGISAWA Masao;TOGAWA Nozomu

Technical report of IEICE. VLD 113(454) p.43 - 482014/02-2014/02

CiNii

Detail

ISSN:0913-5685

Outline:Scan test using scan chains is one of the most important DFT techniques. On the other hand, scan-based attacks are reported which can retrieve the secret key in crypto circuits by using scan chains. Secure scan architecture is strongly required to protect scan chains from scan-based attacks. In this paper, we propose an improved version of random order scans as a secure scan architecture. In our improved random order scans, a scan chain is partitioned into multiple sub-chains. The structure of the scan chain changes dynamically by selecting a subchain to scan out using enable signals. We also discuss testability and security of our improved random order scans and demonstrate their effectiveness through implementation results.

Experiment and Analysis on Temperature Dependence of Delay and Energy for Subthreshold Circuits

KUSHIDA Hiroki;SHI Youhua;TOGAWA Nozomu;USAMI Kimiyoshi;YANAGISAWA Masao

Technical report of IEICE. VLD 113(454) p.147 - 1512014/02-2014/02

CiNii

Detail

ISSN:0913-5685

Outline:Low voltage design has been used in order to reduce the energy dissipation of mobile network equipment. However, as supply voltage reduces into subthreshold region, performance degradation and environment variations become the primary design challenges. In this paper, we implemented a super-pipelined multiplier for subthreshold supply voltage. With super-pipeline, the performance and energy efficiency can be improved. Moreover, experimental evaluations on the temperature dependences of delay and energy are also conducted for analysis.

A Hardware Trojan Detection Method based on Trojan Net Features

2015(28) p.1 - 62015/01-2015/01

CiNii

Detail

ISSN:09196072

Outline:Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry. This circumstance introduces risks that malicious attackers can implement Hardware Trojans (HTs) on them. Partic ularly HTs can be easily inserted during design phase but their detection is too difficult during this phase. This is why we have to assume Golden Netlists and activation of HTs in previous researches. This paper proposes an HT detection method based on Trojan net features. Most of nets in HTs have several features and our method detects the nets having these features. Our approach does not assume Golden netlists nor activation of HTs. We can succesfully detect a Trojan net in each of the HT-inserted gate-level netlists from the Trust-HUB benchmark. It takes approximately thirty minutes to detect Trojan nets in each benchmark.

Suspicious timing error prediction using check points

IGARASHI Hiroaki;SHI Youhua;YANAGISAWA Masao;TOGAWA Nozomu

IEICE technical report. Dependable computing 113(321) p.39 - 442013/11-2013/11

CiNii

Detail

ISSN:0913-5685

Outline:Due to advance process technologies, timing design of LSIs has become more difficult and the importance of timing error countermeasure techniques is increasing as well. Existing timing error detection/correction methods have difficulties in timing design since they have complex structure. Furthermore, their error correction is realized by re-run operation which results in low throughput. We have proposed a suspicious timing error prediction method (STEP method) which predicts timing error and corrects it with simple structure. STEP is based on checking timing errors by observing several checkpoints on signal paths. Since STEP is a timing error prediction method, we may have false positives and reduction of them is one of the largest problems. In this paper, we propose a method to reduce the false positives to optimize the checkpoints. The experimental results show that an operational frequency is increased by up to 2.4 times and its throughput is improved by up to 45%.

Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture

ABE Shin-ya;SHI Youhua;USAMI Kimiyoshi;YANAGISAWA Masao;TOGAWA Nozomu

IEICE technical report. Dependable computing 113(321) p.263 - 2682013/11-2013/11

CiNii

Detail

ISSN:0913-5685

Outline:In this paper, we propose a clock energy-efficient high-level synthesis algorithm for HDR-mcd architecture. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay is required and should be considered during high-level synthesis. In our iterative improvement based algorithm, low-frequency clocks are assigned to non-critical huddles under resource and latency constraints for energy efficiency improvement. Experimental results show that the proposed method achieves 20% clock energy-saving and 10% total energy-saving compared with the existing methods considering clock gating.

AES Encryption Circuit against Clock Glitch based Fault Analysis

2015(10) p.1 - 52015/05-2015/05

CiNii

Detail

ISSN:09196072

Outline:Recently, fault analysis has attracted a lot of attentions as a new kind of side channel attack methods, in which malicious faults are generally injected by attackers through clock glitch generation, voltage change, or laser manipulation during the execution of a crypto circuit. As existing countermeasures against fault analysis, area-redundant and time-redundant methods have been proposed. However they will cause large area overhead or time overhead. Therefore, in this paper, we proposed an AES circuit design that can detect timing faults caused by malicious clock glitches. Experimental results show that the proposed method can detect 100% timing faults at only 4.9% post-layout area overhead.

Design of Flip-Flop with Timing Error Tolerance

SUZUKI Taito;SHI Youhua;TOGAWA Nozomu;USAMI Kimiyoshi;YANAGISAWA Masao

Technical report of IEICE. VLD 114(328) p.45 - 502014/11-2014/11

CiNii

Detail

ISSN:0913-5685

Outline:Under the influence of the miniaturization of the integrated circuit, the variation of the operation condition of the circuit becomes bigger, and margins of the supply voltage and the clock frequency necessary for a design increase. For the mitigation of the margin, the structure of the circuit with the timing error tolerance is studied flourishingly. In this paper, we propose two new Time Borrowing Flip-Flops (TBFF) in transistor level to realize timing error tolerance by switching from flip-flop to latch dynamically. HSPICE simulation results show that the proposed TBFF can achieve up to 28.1% power reduction when compared with existing works.

Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits

KAWAMURA Kazushi;ABE Shinya;SHI Youhua;YANAGISAWA Masao;TOGAWA Nozomu

Technical report of IEICE. VLD 114(328) p.51 - 562014/11-2014/11

CiNii

Detail

ISSN:0913-5685

Outline:The propagation delay along each path inside an LSI widely varies depending on input data, and this property can be exploited to design high-performance approximation circuit with a negligible error rate. In this paper, we propose a novel approximation circuit design algorithm, which identifies paths to be optimized based on input data and reconfigures these paths. Our algorithm first identifies the optimized paths by incorporating timing error prediction circuits into a target circuit and running them in practice. These paths are then dynamically reconfigured within an accuracy constraint with the objective of maximizing its performance. Experimental results targeting a set of basic adders show that our algorithm can achieve performance increase by up to 18.5% within acceptable error of 2.1% compared with conventional design techniques.

An Effective Robust Design Using Improved Checkpoint Insertion Algorithm for Suspicious Timing-Error Prediction Scheme and its Evaluations

YOSHIDA Shinnosuke;SHI Youhua;YANAGISAWA Masao;TOGAWA Nozomu

Technical report of IEICE. VLD 114(328) p.57 - 622014/11-2014/11

CiNii

Detail

ISSN:0913-5685

Outline:As process technologies advance, process and delay variation causes a complex timing design and in-situ timing error correction techniques are strongly required. Suspicious timing error prediction (STEP) predicts timing errors by monitoring checkpoints by STEP circuits (STEPCs) and how to insert checkpoints is very important. We have proposed a network-flow-based checkpoint insertion algorithm for STEP. However, our algorithm may ignore long paths and insert checkpoints near the output. In this paper, we improve how to ignore short paths and set labels by estimating path lengths. Then, we can ignore only short paths and insert checkpoints into near the center of all long paths. We evaluate our algorithm by applying it to four benchmark circuits. Experimental results show that our proposed algorithm realizes an average of 1.71X overclocking compared with just inserting no STEPC. Furthermore, our improved algorithm realizes an average of 1.15X overclocking compared with our original algorithm.

High speed design of sub-threshold circuit by using DTMOS

FUKUDOME Yuji;SHI Youhua;TOGAWA Nozomu;USAMI Kimiyoshi;YANAGISAWA Masao

Technical report of IEICE. VLD 114(328) p.117 - 1212014/11-2014/11

CiNii

Detail

ISSN:0913-5685

Outline:Low power consumption is achieved by operating circuits in sub-threshold region. However, in subthreshold region, the operating speed becomes slow, and the tradeoff between power and speed should be considered carefully. In this work, we present DTMOS implementations to realize high speed and low power in subthreshold region. Transistor level simulation results show that the operating speed can be improved by 30 %-45 %, and on average 15 % energy reduction can be achieved when V_

ranges 0.2-0.3V.

A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists

OYA Masaru;SHI Youhua;YANAGISAWA Masao;TOGAWA Nozomu

Technical report of IEICE. VLD 114(328) p.135 - 1402014/11-2014/11

CiNii

Detail

ISSN:0913-5685

Outline:Recently, digital ICs are designed by outside vendors to reduce design costs in semiconductor industry. This circumstance introduces risks that malicious attackers implement Hardware Trojans (HTs) into ICs. HTs are easily inserted in particular during design phase, but HTs detection is too difficult during this phase. This is why we have to assume Golden Netlists and activation of HTs in previous researches. This paper proposes an HT detection method through detecting LSLG nets, which have low switching probabilities. Our approach does not assume Golden netlists nor activation of HTs. We succesfully find out that all HT-inserted gate-level netlists from Trust-HUB benchmarks include a small number of LSLG nets. It takes approximately ten minutes to detect LSLG nets in each benchmark.

Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages

ABE Shin-ya;SHI Youhua;USAMI Kimiyoshi;YANAGISAWA Masao;TOGAWA Nozomu

Technical report of IEICE. VLD 114(328) p.203 - 2082014/11-2014/11

CiNii

Detail

ISSN:0913-5685

Outline:An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis and enables us to estimate interconnection delay effects during high-level synthesis, has been proposed with the corresponding synthesis algorithm. They assign voltages and clock frequencies to huddles which are the partitions for interconnection delay estimation during high-level synthesis. However, the voltage and clock assignment may have some energy overheads due to the increased clock trees. In this paper, we propose a new HDR-mcv architecture in which supply voltages are assigned to functional logics and clock synchronization logics separately. Next, we propose a high-level synthesis algorithm for the architecture, which can assign clock frequencies and supply voltages on the bases of the placement and energy informations. Experimental results show that the proposed method achieves 50% energy-saving compared with the conventional HDR-mcv architecture and 60% energy-saving compared with the existing high-level synthesis methods.

A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists

OYA Masaru;SHI Youhua;YAMASHITA Noritaka;OKAMURA Toshihiko;TSUNOO Yukiyasu;GOTO Satoshi;YANAGISAWA Masao;TOGAWA Nozomu

IEICE Trans. Fundamentals 98(12) p.2537 - 25462015-2015

CiNii

Detail

ISSN:0916-8508

Outline:Outsourcing IC design and fabrication is one of the effective solutions to reduce design cost but it may cause severe security risks. Particularly, malicious outside vendors may implement Hardware Trojans (HTs) on ICs. When we focus on IC design phase, we cannot assume an HT-free netlist or a Golden netlist and it is too difficult to identify whether a given netlist is HT-free or not. In this paper, we propose a score-based hardware-trojans identifying method at gate-level netlists without using a Golden netlist. Our proposed method does not directly detect HTs themselves in a gate-level netlist but it detects a net included in HTs, which is called Trojan net, instead. Firstly, we observe Trojan nets from several HT-inserted benchmarks and extract several their features. Secondly, we give scores to extracted Trojan net features and sum up them for each net in benchmarks. Then we can find out a score threshold to classify HT-free and HT-inserted netlists. Based on these scores, we can successfully classify HT-free and HT-inserted netlists in all the Trust-HUB gate-level benchmarks and ISCAS85 benchmarks as well as HT-free and HT-inserted AES gate-level netlists. Experimental results demonstrate that our method successfully identify all the HT-inserted gate-level benchmarks to be "HT-inserted" and all the HT-free gate-level benchmarks to be "HT-free" in approximately three hours for each benchmark.

A-9-2 Low-power soft-error tolerant New-SEH latch scheme

TAJIMA Saki;SHI Youhua;TOGAWA Nozomu;YANAGISAWA Masao

Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference 20152015/08-2015/08

CiNii

Detail

ISSN:2189700X

Timing Monitoring Paths Selection for Wide Voltage IC

Shan Weiwei;Dai Wentao;Shi Youhua;Cao Peng;Xiang Xiaoyan

IEICE Electronics Express 0(0) 2016-2016

CiNii

Detail

ISSN:1349-2543

Outline:Wide voltage range circuit has got widespread attention where in-situ timing monitoring based adaptive voltage scaling (AVS) becomes necessary to reduce the design margin. However, the severe PVT variations across near-threshold to super-threshold cause too many critical paths to be monitored. Here activation oriented monitoring paths selection method is proposed to reduce the monitored paths for wide voltage IC. The minimum delay value of the longest activated path is found by dynamic timing analysis and set as the selection threshold. Those paths longer than this threshold by STA analysis are selected to be monitored. Applied on a 40nm AVS System-on-Chip, it reduces the monitoring paths to only 22% of all critical paths with remarkable power gains under 0.6V-1.1V.

Lecture And Oral

A Score-Based Classification Method for Identifying Hardware-Trojans Inserted/Free Gate-Level Netlists

Design, Automation & Test in Europe (DATE)2015/03/11

Detail

Oral presentation(general)

Secure Scan Design Using Improved Random Order and its Evaluations

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)2014/11/19

Detail

Poster presentation

An Area-Overhead-Oriented Monitoring-Path Selection Algorithm for Suspicious Timing Error Prediction

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)2014/11/19

Detail

Oral presentation(general)

In-situ Timing Monitoring Methods for Variation-Resilient Designs

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)2014/11/20

Detail

Oral presentation(general)

InTimeTune: A Throughput Driven Timing Speculation Architecture for Overscaled Designs

ACM/EDAC/IEEE Design Automation Conference2014/06/04

Detail

Poster presentation

Throughput Driven Check Point Selection in Suspicious Timing Error Prediction based Designs

IEEE Latin American Symposium on Circuits and Systems (LASCAS)2014/02/27

Detail

Oral presentation(general)

Secure Scan Design with Dynamically Configurable Connection

IEEE Pacific Rim International Symposium on Dependable Computing2013/12/04

Detail

Oral presentation(general)

Predication based Timing Speculation Technique for Throughput Improvement

International Conference on Integrated Circuits, Design, and Verification2013/11/16

Detail

Oral presentation(general)

Floorplan Driven Architectures and High-level Synthesis Algorithm for Dynamic Multiple Supply Voltages

ACM/EDAC/IEEE Design Automation Conference2013/06/05

Detail

Poster presentation

Concurrent Faulty Clock Detection for Crypto Circuits Against Clock Glitch Based DFA

IEEE International Symposium on Circuits and Systems2013/05/21

Detail

Oral presentation(general)

DR24 An Energy-efficient High-level Synthesis Algorithm Incorporating Interconnection Delays and Dynamic Multiple Supply Voltages

IEEE International Symposium on VLSI Design, Automation and Test2013/04/22

Detail

Oral presentation(general)

Suspicious Timing Error Detection and Recovery with In-Cycle Clock Gating

IEEE International Symposium on Quality Electronic Design (ISQED)2013/03/05

Detail

Poster presentation

State Dependent Scan Flip-Flop with Key-Based Configuration against Scan-Based Side Channel Attack on RSA Circuit

IEEE Asia Pacific Conference on Circuits and Systems2012/12/05

Detail

Oral presentation(general)

Dynamically Changeable Architecture against Scan-Based Side Channel, Attack Using State Dependent Scan Flip-Flop on RSA Circuit

IEEE International SoC Design Conference2012/11/06

Detail

Oral presentation(general)

Research Grants & Projects

Grant-in-aids for Scientific Research Adoption Situation

Research Classification:

Research on delay test techniques for ultra-low power designs

2011-2013

Allocation Class:¥4420000

Research Classification:

Design Methods for Crypto LSI Implementations and Testing

2009-2011

Allocation Class:¥4680000

Research Classification:

Automatic False Path Identification and Test Synthesis System Development to Avoid Overtesting

2007-2009

Allocation Class:¥3770000

On-campus Research System

Special Research Project

システムオンチップのテスト容易化設計に関する研究

2005

Research Results Outline:LSIの超大規模化・超微細化により、情報システム全体をワン・チップ上に実現することが可能になった。しかし、高集積化により故障をチェックするべき点が増えLSIの超大規模化・超微細化により、情報システム全体をワン・チップ上に実現することが可能になった。しかし、高集積化により故障をチェックするべき点が増え、各点の故障をテストするパターンの数は増加し、製造されたチップが正常に動作するか否かを調べるテスト...LSIの超大規模化・超微細化により、情報システム全体をワン・チップ上に実現することが可能になった。しかし、高集積化により故障をチェックするべき点が増え、各点の故障をテストするパターンの数は増加し、製造されたチップが正常に動作するか否かを調べるテストは益々困難になってきている。1チップあたりのテスト時間はテスト・パターンの数に比例するので、機能モジュールを複数集積したシステムオンチップ(SoC,System-on-a-Chip)では、集積したモジュールの数に比例した時間がかかり、テストの時間が非常に長くなる。その結果、SoCのテスト・コストが製造コストを超える勢いで増加しており、テストの品質も低下しているため、テストは半導体産業の発展を阻害する要因になりかねない。そのために、SoCに関する低コスト、高品質なテスト容易化設計方法の研究が重要となってきた。上記背景のもと,本研究ではテスト・データの圧縮技術やテスト時間削減の容易化設計手法に関する研究を行う。提案手法ではデザインに挿入され、少ないスキャン・チャネルから多数の内部スキャン・チェーンを供給するデコンプレッサで構成される。最先端のスキャンおよびテスト・データの圧縮技術と比較し、テスト・データの量とテスト時間を最大20 分の1までに削減できる。その研究成果を学会において発表した。また、多種の故障タイプのテストに対応し、故障解析方法の詳細の検討を行った.

ディペンタブルな低電圧LSI設計技術に関する研究

2011

Research Results Outline: 情報通信機器が高性能化するにしたがい、消費電力の増大が大きな問題になりつつある。LSI回路の低消費電力化には、LSI の電源電圧を下げることが最も効 情報通信機器が高性能化するにしたがい、消費電力の増大が大きな問題になりつつある。LSI回路の低消費電力化には、LSI の電源電圧を下げることが最も効果的である。CMOS回路の動作電力は電圧の自乗に比例するので、電圧を1/3にすれば、単純には消費電... 情報通信機器が高性能化するにしたがい、消費電力の増大が大きな問題になりつつある。LSI回路の低消費電力化には、LSI の電源電圧を下げることが最も効果的である。CMOS回路の動作電力は電圧の自乗に比例するので、電圧を1/3にすれば、単純には消費電力がほぼ1/10 になる。しかし、低電圧の条件下ではCMOS回路の動作が不安定になり、LSIの製造ばらつきやノイズなどに影響され、動作マージン減少、誤動作などの障害が、現状と比較して極めて増大する。つまり将来安心かつエコなアンビエント情報社会を実現するためには、情報通信・処理の主要素子であるCMOS トランジスタの動作電圧をしきい値電圧以下に低減できるLSI自動化設計技術と高信頼化設計技術の統合・融合したディペンタブルな低電圧LSI設計基盤技術が強く求められると考える。 本研究は、高い信頼性を持つディペンタブルな超低電圧LSI設計技術の開発を目的とする。研究の目標としては、既存研究(カスタム設計)と異なり、自動化設計により、設計複雑度や設計周期を減らし、並びに回路全体の信頼性を高めることを目指す。また、実チップ設計により、既存研究と比較してエネルギーを低減し、並びに低電圧領域における設計タイミングのばらつきを改善することを目標とする。 今年度では、主に以下の研究項目を行ってきた。(1)超低電圧LSI自動化設計技術について 具体的には、低電圧領域(サブスレッショルド領域)で動作する回路設計のため、①サブスレッショルド領域での遅延・電力のモデルの構築;②サブスレッショルド領域で動作させるため、既存のプロセスライブラリを用いて、トランジスタレベルでシミュレーションを行い、エネルギーが最小な電源電圧を選択できる合成手法の提案、及び③提案した最適エネルギー電圧選択手法をベースに上位レベル(RTLレベル)から低電圧による低エネルギー指向LSI自動合成フローの構築などの研究を取り込んだ。様々なアルゴリズムをコンピュータに実装し、評価実験を行った。既存のカスタム設計と異なり、合成時自動でエネルギー最小な電源電圧の選択ができ、Benchmark回路に適用し有効性を確認した。また、自動化設計により、設計複雑度や設計周期を減らすごとができた。(2)ディペンタブルなLSI設計技術について  具体的には、①LSI回路動作時の遅延、温度変化および電源電圧変化の解析、及び②電圧変動により、ディレイ変動を検出・制御する技術の研究を行った。研究成果として、理論面から、80%以上の論理パス上発生した遅延エーラの検出ができた。

自然エネルギー利用に向けたスマートケースLSI設計技術の創生

2014

Research Results Outline: 本研究ではLSI(大規模集積回路)の設計技術に焦点を当て、不安定且つ微弱な自然エネルギーに適合し、状況に応じた最適な動作を実現するスマートケースLS 本研究ではLSI(大規模集積回路)の設計技術に焦点を当て、不安定且つ微弱な自然エネルギーに適合し、状況に応じた最適な動作を実現するスマートケースLSI設計技術の研究開発を行った。特に、既存LSI設計技術の問題点を解決する革新的技術として「I: 極... 本研究ではLSI(大規模集積回路)の設計技術に焦点を当て、不安定且つ微弱な自然エネルギーに適合し、状況に応じた最適な動作を実現するスマートケースLSI設計技術の研究開発を行った。特に、既存LSI設計技術の問題点を解決する革新的技術として「I: 極低エネルギーLSI設計技術」と「II:動作中自己調整機能を持つ設計技術」を提案した。本研究は、既存のワーストケースに基づいたLSI設計方法ではなく、回路が動作時自己調整により処理性能・消費電力・信頼性を最大限引き出すことが可能なシステムLSI設計基盤技術を開発した。

Lecture Course

Course TitleSchoolYearTerm
Introduction to Electronic and Physical SystemsSchool of Fundamental Science and Engineering2017spring semester
Introduction to Electronic and Physical Systems [S Grade]School of Fundamental Science and Engineering2017spring semester
Electronic and Physical Systems Practice ASchool of Fundamental Science and Engineering2017spring semester
Electronic and Physical Systems Practice A [S Grade]School of Fundamental Science and Engineering2017spring semester
Electronic and Physical Systems Practice BSchool of Fundamental Science and Engineering2017fall semester
Electronic and Physical Systems Practice B [S Grade]School of Fundamental Science and Engineering2017fall semester
Electronic and Physical Systems Laboratory ASchool of Fundamental Science and Engineering2017fall semester
Electronic and Physical Systems Laboratory A [S Grade]School of Fundamental Science and Engineering2017fall semester
Electronic DevicesSchool of Fundamental Science and Engineering2017spring semester
Electronic Devices [S Grade]School of Fundamental Science and Engineering2017spring semester
Electronic and Physical Systems Practice CSchool of Fundamental Science and Engineering2017spring semester
Electronic and Physical Systems Practice C [S Grade]School of Fundamental Science and Engineering2017spring semester
Electronic and Physical Systems Laboratory BSchool of Fundamental Science and Engineering2017spring semester
Electronic and Physical Systems Laboratory B [S Grade]School of Fundamental Science and Engineering2017spring semester
Electronic and Physical Systems Laboratory CSchool of Fundamental Science and Engineering2017fall semester
Electronic and Physical Systems Laboratory C [S Grade]School of Fundamental Science and Engineering2017fall semester
Special Seminar on Electronic and Physical SystemsSchool of Fundamental Science and Engineering2017fall semester
Electronic and Physical Systems Practice CSchool of Fundamental Science and Engineering2017spring semester
Electronic and Physical Systems Practice C [S Grade]School of Fundamental Science and Engineering2017spring semester
Bachelor Thesis ASchool of Fundamental Science and Engineering2017spring semester
Bachelor Thesis A [S Grade]School of Fundamental Science and Engineering2017spring semester
Bachelor Thesis BSchool of Fundamental Science and Engineering2017fall semester
Bachelor Thesis B [S Grade]School of Fundamental Science and Engineering2017fall semester
Electronic CircuitsSchool of Fundamental Science and Engineering2017fall semester
Electronic CircuitsSchool of Fundamental Science and Engineering2017fall semester
Electronic CircuitsSchool of Fundamental Science and Engineering2017fall semester
Electronic CircuitsSchool of Fundamental Science and Engineering2017fall semester
Research Project ASchool of Fundamental Science and Engineering2017fall semester
Master's Thesis (Department of Electronic and Physical Systems)Graduate School of Fundamental Science and Engineering2017full year
Research on Integrated System DesignGraduate School of Fundamental Science and Engineering2017full year
System LSI design and CADGraduate School of Fundamental Science and Engineering2017fall semester
System LSI design and CADGraduate School of Fundamental Science and Engineering2017fall semester
System LSI design and CADGraduate School of Fundamental Science and Engineering2017fall semester
Seminar on Integrated System Design AGraduate School of Fundamental Science and Engineering2017spring semester
Seminar on Integrated System Design BGraduate School of Fundamental Science and Engineering2017fall semester
Seminar on Integrated System Design CGraduate School of Fundamental Science and Engineering2017spring semester
Seminar on Integrated System Design DGraduate School of Fundamental Science and Engineering2017fall semester
Research on Integrated System DesignGraduate School of Fundamental Science and Engineering2017full year